| SIGNAL
|
I/O |
DESCRIPTION |
|
OSC |
O |
Oscillator: High-speed clock with a 70-ns period (14.31818 MHz). It
has a 50% duty cycle. |
|
CLK |
O |
System Clock: It is a divide-by-three of the oscillator and has a
period of 210 ns(4.77 MHz).The clock has a 33% duty cycle. |
|
RESET DRV |
O |
This line is used to reset or initialize system logic upon power-up
or during a low line voltage outage. This signal is synchronized to the
falling edge of clock and is active high. |
|
A0-A19 |
O |
Address bits 0 to 19 : These lines are used to address memory and
I/O devices within the system. The 20 address lines allow access of up
to 1 megabyte of memory. A0 is the least significant bit (LSB) and A19
is the most significant bit (MSB).These lines are generated by either
the processor or DMA controller. They are active high. |
|
D0-D7 |
I/O |
Data Bits 0 to 7 : These lines provide data bus bits 0 to 7 for the
processor, memory, and I/O devices. D0 is the least significant bit
(LSB) and D7 is the most significant bit (MSB). These lines are active
high. |
|
ALE |
O |
Address Latch Enable : This line is provided by the 8288 Bus
Controller and is used on the system board to tatch valid addresses from
the processor. It is available to the I/O channel as an indicator of a
valid processor address (when used with AEN). Processor addresses are
latched with the falling edge of ALE |
|
I/O CH CK |
I |
-I/O Channel Check : This line provides the processor with parity
(error) information on memory or devices in the I/O channel. When this
signal is active low , a parity error is indicated. |
|
I/O CH RDY |
I |
I/O Channel Ready : This line, normally high (ready), is pulled low
(not ready) by a memory or I/O device to lengthen I/O or memory cycles.
It allows slower devices to attach to the I/O channel with a minimum of
difficulty. Any slow device using this line should drive it low
immidiately upon detecting a valid address and a read or write command.
This line should never be held low longer than 10 clock cycles. Machine
clcles (I/O or memory) are extened by an integral number of CLK
cycles(210 ns). |
|
IRQ2-IRQ7 |
I |
Interrupt Request 2 to 7: This line s are used to signal the
processor that an I/O device requires attention. They are prioritized
with IRQ2 as the highest priority and IRQ7 as the lowest. An Interrupt
Request is generated by raising an IRQ line (low to high) holding it
high until it is acknowledged by the processor (interrupt service
routine). |
|
IOR |
O |
-I/O Read Command : This Command line Instructs an I/O devices to
drive its data onto the data bus. It may be driven by the processor or
the DMA controller. This signal is active low. |
|
IOW |
O |
-I/O Write Command :This Command line Instructs an I/O devices to
read the data on the data bus. It may be driven by the processor or the
DMA controller. This signal is active low. |
|
MEMR |
O |
Memory Read Command :This Command line Instructs the memory to drive
its data onto the data bus. It may be driven by the processor or the DMA
controller. This signal is active low. |
|
MEMW |
O |
Memory WriteCommand :This Command line Instructs the memory to store
the data present on the data bus. It may be driven by the processor or
the DMA controller. This signal is active low. |
|
DRQ1-DRQ3 |
I |
DMA Request 1 to 3 : These lines are asynchronous channel requests
used by peripheral devices to gain DMA service. They are prioritized
with DRQ3 being the lowest and DRQ1 being the highest. A request is
generated by bringing a DRQ line to an active level (high). A DRQ line
must be held high until the corresponding DACK line goes active. |
|
DACK0-DACK3 |
O |
-DMA Acknowledge 0 to 3 : These lines are used to acknowledge DMA
requests (DRQ1-DRQ3) and to refresh system dynamic memory (DACK0). They
are active low. |
|
AEN |
O |
Address Enable : this line is used to de-gate the processor and
other devices from the I/O channel to allow DMA transfers to take place.
When this line is active (high), the DMA controller has control of the
address bus, data bus, read command lines (memory and I/O), and the
write command lines (memory and I/O). |
|
T/C |
O |
Terminal Count : This line provide a pulse when the terminal count
for any DMA channel is reached. This signal is active high. |
|
CARD SLCTD |
I |
-Card Selected : This line is activated by cards in expansion slot.
It signals the system board that the card has been selected and that
appropriate drivers on the system board should be directed to either
read from , or write to , expansion slot. This line from expansion slot
1 to 8 aer tied together at this pin, but the system board dose not use
their signal. This line should be driven by an open collector device.
|